Signaling protocol conversion between a processor and a...

Details Signaling protocol conversion between a processor and a... Signaling protocol conversion between a processor and a...

G - Physics

06

F

G06F 15/163 (2006.01) G06F 13/364 (2006.01)

Patent

CA 2209157

-35- A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on thepipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

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