Simple fault tolerance for memory

Details Simple fault tolerance for memory Simple fault tolerance for memory

G - Physics

06

F

G06F 11/20 (2006.01) G11C 29/00 (2006.01)

Patent

CA 2435396

Methods and an associated apparatus are disclosed for providing fault tolerance for memory. The method involves producing a remapping value (202). Then the remapping value may be logically combined with the address value intended for accessing a given memory location (204) to remap the bad address to the unused address. The remapped address may then be accessed in place of an intended address (206).

L'invention concerne des procédés ainsi qu'un appareil associé assurant une tolérance aux défaillances à une mémoire. Le procédé consiste à produire une valeur de reconfiguration (202). Ensuite, la valeur de reconfiguration peut être combinée logiquement à la valeur d'adresse destinée à permettre d'accéder à un emplacement mémoire donné (204) afin de reconfigurer la mauvaise adresse sur l'adresse inutilisée. L'accès à l'adresse reconfigurée est alors possible à la place d'une adresse prévue (206).

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