G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/14 (2006.01) G11C 7/00 (2006.01)
Patent
CA 2358332
Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size. Within each frame, the read addresses to be accessed by read memory operations can be rearranged to minimize memory bank access conflicts with either write addresses to be accessed by write memory operations or other read addresses. 1
Chen Jason
Chow Henry
Janoska Mark William
Chen Jason
Pmc-Sierra Ltd.
Shapiro Cohen
LandOfFree
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