H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/30
H01L 21/74 (2006.01) H01L 21/22 (2006.01) H01L 21/76 (2006.01) H01L 21/761 (2006.01) H01L 21/8228 (2006.01) H01L 27/082 (2006.01)
Patent
CA 1053376
SIMPLIFIED COMPLEMENTARY TRANSISTOR PROCESS FOR MAKING ENHANCED GAIN LATERAL TRANSISTOR Abstract of the Disclosure A process for producing simultaneously an NPN vertical bi- polar transistor and a PNP lateral bipolar transistor on a re- cessed oxide-isolated epitaxial layer. An N+ buried layer is placed in the P- substrate beneath each transistor. P+ regions then are placed in the substrate underneath (or optionally in lieu of) the later formed recessed oxide and underneath the emitter region of each later formed lateral transistor. An N type epitaxial layer is deposited over the structure and the previously formed N+ and P+ substrate regions are outdiffused into the epitaxial layer, the P+ regions outdiffusing to a greater extent. Recessed oxide iso- lation walls are made and P+ areas are introduced into the epitaxial layer to form the base of each NPN transistor and to form a collector and an extended depth emitter for each PNP transistor, said emitter reaching from the surface of the epitaxial layer to the underlying N+ buried layer. The transistors are completed in the usual manner.
266527
Antipov Igor
Calhoun Harry C.
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