Single bus graphics data processing pipeline

Details Single bus graphics data processing pipeline Single bus graphics data processing pipeline

G - Physics

06

F

354/230.87

G06F 9/44 (2006.01) G06F 13/368 (2006.01) G06T 1/20 (2006.01)

Patent

CA 1329431

Abstract of the Disclosure Stages of a graphics data processing pipeline are interconnected by a common bus far conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus. When the sending stage determines from the state of the BUSY bit that the next stage is ready to receive input data, the sending stage acquires control of the bus and sends the input data thereon to the next stage.

608620

Affiliated with

Also associated with

Rating

Single bus graphics data processing pipeline does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single bus graphics data processing pipeline, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single bus graphics data processing pipeline will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1271436