Single chip microcomputer selectively operable in response...

Details Single chip microcomputer selectively operable in response... Single chip microcomputer selectively operable in response...

G - Physics

06

F

354/230.7

G06F 9/24 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1137641

ABSTRACT OF THE DISCLOSURE A microprocessor external instruction feature which pro- vides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruc- tion store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An external instruction mode input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 external instruction (XI) input pins instead of from the on-chip ROS. A branch decision output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external in- struction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A wait output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state. SA9-78-071

349769

Affiliated with

Also associated with

Rating

Single chip microcomputer selectively operable in response... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single chip microcomputer selectively operable in response..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single chip microcomputer selectively operable in response... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-554478