Single chip vlsi implementation of a digital receiver...

Details Single chip vlsi implementation of a digital receiver... Single chip vlsi implementation of a digital receiver...

H - Electricity

04

L

H04L 27/26 (2006.01) G06F 17/14 (2006.01) H04L 1/00 (2006.01) H04L 25/02 (2006.01)

Patent

CA 2270149

The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequecy control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

L'invention concerne une implémentation monopuce d'un récepteur numérique pour signaux à porteuses multiples émis par multiplexage en fréquence orthogonal. Elle améliore l'estimation des canaux et la correction des circuits. Le récepteur comporte des circuits de haute précision pour la commande de la fréquence d'échantillonnage et la commande de la fréquence. Le décodage BCH des porteuses de données tps se fait avec des ressources minimales au moyen d'un arrangement qui comprend un petit multiplicateur de corps de Galois. Un circuit de synchronisation à fenêtre FFT perfectionné est couplé au circuit de rééchantillonnage, de façon à localiser la limite de l'intervalle de garde émis avec la trame active du signal. Un processeur FFT pipeline en temps réel, fonctionnellement associé au circuit de synchronisation, fonctionne avec un encombrement mémoire réduit.

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