Single polycrystalline silicon memory cell

Details Single polycrystalline silicon memory cell Single polycrystalline silicon memory cell

H - Electricity

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H01L 23/48 (2006.01) G11C 11/412 (2006.01) H01L 23/522 (2006.01) H01L 27/06 (2006.01) H01L 27/11 (2006.01)

Patent

CA 1149950

SINGLE POLYCRYSTALLINE SILICON MEMORY CELL ABSTRACT OF THE DISCLOSURE A single polycrystalline silicon configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first-conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

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