Single rail domino logic for four-phase clocking scheme

Details Single rail domino logic for four-phase clocking scheme Single rail domino logic for four-phase clocking scheme

H - Electricity

03

K

H03K 19/0175 (2006.01) H03K 19/096 (2006.01)

Patent

CA 2338114

A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.

L'invention concerne un circuit logique en domino à pôle unique fonctionnant avec un type de cadencement en quatre phase. Deux PMOS superposés produisent un temps de précharge de cycle par quart d'horloge. Ce temps de précharge permet de placer un inverseur supplémentaire dans la voie de signaux de sortie pour constituer un signal de sortie et un complément de signal de sortie destinés à être utilisés dans des étapes logiques subséquentes.

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