Single transistor electrically programmable memory device...

G - Physics – 11 – C

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356/128, 352/82.

G11C 17/00 (2006.01) G11C 16/04 (2006.01) G11C 16/10 (2006.01) G11C 16/16 (2006.01) H01L 21/28 (2006.01) H01L 21/321 (2006.01) H01L 21/336 (2006.01) H01L 27/10 (2006.01) H01L 27/115 (2006.01) H01L 29/08 (2006.01) H01L 29/51 (2006.01) H01L 29/788 (2006.01)

Patent

CA 1236919

Abstract of the Disclosure Single Transistor Electrically Programmable Memory Device And Method An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

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