Slave-type interface circuit operating with a series bus

Details Slave-type interface circuit operating with a series bus Slave-type interface circuit operating with a series bus

G - Physics

06

F

354/231

G06F 13/42 (2006.01) G06F 1/04 (2006.01)

Patent

CA 1229419

18 ABSTRACT: The invention relates to a slave-type interface cir- cuit operating with a series bus in a configuration in which writing takes place after recognition of an address. A cycle transmitted by the bus contains an address sequence and a data sequence. The circuit controls a plurality of user circuits (COM) on the basis of data stored in a memory (M) and of a decoder (CDEC). A register (REG) and a bus logic (BUSL) receive at their inputs (L1, L2) information (SDA) and clock (SCL) signals, The bus logic (BUSL) receives from identification circuit (AIC) a signal (DVA) indicating whether or not the address transmitted by the bus correspond to an address A0, A1, A2 displayed at the inputs S0, S1 and S2. It controls the circuit on the basis of the register (REG) initialisation signal (RSTL), a signal (LDS) for the authorisation of the loading of data into the memory (M) and an acceptance signal (ACK) transmitted in the direction of the bus.

483310

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