Spare cell architecture for fixing design errors in...

H - Electricity – 03 – K

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Details

H03K 19/003 (2006.01) G06F 11/20 (2006.01) H03K 19/177 (2006.01)

Patent

CA 2502077

A fully self-sufficient configurable spare gate cell (11) has two types of inputs: a functional input bus (FIN; 10,12; 68; 76) and an equation input bus (EQ.IN; 70; 78), whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. The spare cell may also include a D flip-flop (38; 84). In a spare state, the functional input buses are connected to an area of pre-defined logic (64) where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

La présente invention concerne une cellule de porte de rechange configurable complètement autonome (11) qui présente deux types d'entrée : un bus d'entrée fonctionnel (FIN; 10,12; 68; 76) et un bus d'entrée d'équation (EQ.IN; 70; 78). Cette cellule de porte de rechange peut être transformée en toute somme d'opérateur de produit par assertion de certains signaux au bus d'entrée d'équation. La cellule de rechange peut également comprendre une bascule bistable D (38; 84). A l'état de rechange, les bus d'entrée fonctionnels sont connectés à une zone de logique prédéfinie (64) où les besoins en correction de bogue sont élevés. La cellule de rechange est ainsi placée automatiquement à proximité de la zone de correction de bogue lors de la phase de placement et de routage d'une conception de puce, ce qui permet de réduire le besoin de surveillance des canaux de routage.

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