Speed-tolerant digital decoding system

Details Speed-tolerant digital decoding system Speed-tolerant digital decoding system

G - Physics

11

B

354/67

G11B 20/14 (2006.01)

Patent

CA 1076259

SPEED-TOLERANT DIGITAL DECODING SYSTEM ABSTRACT OF THE DISCLOSURE This disclosure describes a decoding system for decoding and formatting digital data recorded on magnetic tape in the STR ("speed- tolerant recording") format. The digital words are stored in cells of about equal width except that the leading cell of each word, called a "sync" cell, is of double width. Each cell starts with a positive pulse, and a cell detector provides a signal each time this occurs. The apparatus includes a data detector, which analyzes the width of this positive pulse relative to the cell width to determine whether the cell is a "1" bit or a "0" bit. Since the measurement is relative, cell length, i.e., total cell time, is not important. The bit determination is loaded into a shift register. Other apparatus determines the width of the cell, so that a sync cell detector can determine whether a sync cell is present or not. When a sync cell is detected, a pulse is gener- ated which actuates the output buffer register to load the bits from the shift register. Data flows from buffer to a computer.

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