Split buffer architecture

Details Split buffer architecture Split buffer architecture

G - Physics

06

F

G06F 12/06 (2006.01) G06F 5/06 (2006.01) G06F 12/02 (2006.01)

Patent

CA 2223890

A partitioned memory (45) is divided into a number of large buffers (60), and one or more of the large buffers is divided to create an equal number of small buffers (65). Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

Une mémoire cloisonnée (45) est divisée en plusieurs mémoires tampons (60) de grande taille et une ou plusieurs de ces mémoires tampons sont divisées, de manière à créer un nombre égal de petites mémoires tampons (65). Chaque mémoire tampon de grande taille restante est associée à une petite mémoire tampon et on peut accéder à ces mémoires tampons appariées au moyen d'un pointeur unique. Les curseurs sont rangés dans une unité FIFO (premier entré, premier sorti), afin de créer un regroupement de paires de mémoires tampons disponibles.

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