Split phase loop

Details Split phase loop Split phase loop

H - Electricity

03

L

354/231, 328/89

H03L 7/00 (2006.01) H03K 5/15 (2006.01)

Patent

CA 1257341

ABSTRACT An apparatus and method are described for generating a plurality of clock edges from a reference clock signal. The clock edges which are generated are locked in phase with the reference clock signal. The edges may be at any integral or non- integral multiple of the reference clock frequency.

515562

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