Stacked mos devices with polysilicon interconnects

Details Stacked mos devices with polysilicon interconnects Stacked mos devices with polysilicon interconnects

H - Electricity

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H01L 29/76 (2006.01) H01L 21/822 (2006.01) H01L 23/485 (2006.01) H01L 23/532 (2006.01) H01L 27/06 (2006.01)

Patent

CA 1181871

STACKED MOS DEVICES WITH POLYSILICON INTERCONNECTS Abstract of the Disclosure A stacked metal-oxide-semiconductor (MOS) device has a lower source, drain and channel formed in a silicon substrate and an upper source, drain and channel formed in a deposited polysilicon layer which is recrystallized by laser annealing. Instead of the conventional method of depositing aluminum interconnects between the device upper terminals and bonding pads, interconnect parts are formed in the recrystallized polysilicon layer itself. This has the advantages of preventing junction distortion by undesired aluminum penetration into the silicon. Also contact windows do not have to be opened directly to the source and drain terminals thereby easing design constraints. - i -

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