Store buffer device in digital computer system

Details Store buffer device in digital computer system Store buffer device in digital computer system

G - Physics

06

F

354/237

G06F 12/12 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1222061

ABSTRACT OF THE DISCLOSURE A digital computer system including a central processing unit; a main storage unit; a buffer storage unit provided between the central processing unit and the main storage unit and functioning as an effective memory device for the central processing unit with a high speed access time; and a store buffer device provided between the central processing unit and the main storage unit, receiving data identical to that to be stored in the buffer storage unit and control information for the received data in response to requests from the central processing unit and trans- ferring the received data and control information to the main storage unit. The transmission operation from the central processing unit to the store buffer device and transfer operation from the store buffer device to the main storage unit are effected on the basis of a machine cycle timing. The store buffer device includes a controller, a plurality of data register sets, each set including a plurality of data registers for receiving data to be stored in the main storage unit, a byte mark register set forming a plurality of byte mark registers for receiving infor- mation indicating storable data in the data registers, and an address register set forming a plurality of address registers for receiving a starting store address in the main storage unit for the data to be stored in the data registers. The number of data register sets is a plurality of times the bus width of the central processor unit. It is preferable that each byte mark register have a plurality of bits corresponding to the number of data register sets multiplied by the number of bytes of the data register.

469912

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