Strained silicon, gate engineered fermi-fets

H - Electricity – 01 – L

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H01L 21/28 (2006.01) H01L 29/10 (2006.01) H01L 29/78 (2006.01)

Patent

CA 2589539

A field effect transistor includes a strained silicon channel in a substrate, source/drain regions in the substrate at opposite ends of the strained silicon channel, a gate insulating layer on the strained silicon channel, and a gate on the gate insulating layer. The doping of the strained silicon channel, the doping of the substrate and/or the depth of the strained silicon channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the strained silicon channel surface at a threshold voltage of the field effect transistor. Moreover, the gate is configured to provide a gate work function that is close to a mid-bandgap of silicon. Accordingly, a Fermi-FET with a strained silicon channel and a gate layer with a mid-bandgap work function are provided. Related fabrication methods using epitaxial growth also are described.

L'invention concerne un transistor à effet de champ comprenant un canal en silicium contraint dans un substrat, des régions de source/drain dans le substrat aux extrémités opposées du canal en silicium contraint, une couche isolante de grille sur le canal en silicium contraint et une grille sur la couche isolante de grille. Le dopage du canal en silicium contraint, le dopage du substrat et/ou la profondeur du canal en silicium contraint sont étudiés pour produire un champ électrique vertical quasi nul dans la couche isolante de grille et dans la surface du canal en silicium contraint à la tension de seuil du transistor à effet de champ. De plus, la grille est conçue pour assurer une fonction de grille proche d'une bande interdite moyenne de silicium. On dispose ainsi d'un transistor à effet de champ de Fermi avec canal en silicium contraint et couche de grille avec fonctions de bande interdite moyenne. Sont également décrits des procédés de fabrication par croissance epitaxiale.

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