H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128, 356/146
H01L 21/76 (2006.01) B05D 5/12 (2006.01) H01L 21/28 (2006.01) H01L 21/321 (2006.01) H01L 21/336 (2006.01) H01L 21/768 (2006.01) H01L 23/532 (2006.01) H01L 29/49 (2006.01)
Patent
CA 1092726
STRUCTURE AND FABRICATION METHOD FOR INTEGRATED CIRCUITS WITH POLYSILICON LINES HAVING LOW SHEET RESISTANCE ABSTRACT OF THE DISCLOSURE A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.
308257
International Business Machines Corporation
Na
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