Structured logic array

Details Structured logic array Structured logic array

G - Physics

06

F

354/221

G06F 9/00 (2006.01) H03K 19/17 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1167170

STRUCTURED LOGIC ARRAY Abstract of the Disclosure The present invention relates to a programmed logic array for processing binary input signals to produce binary output signals. The programmed logic array is comprised of a first logic array having a plurality of input lines for receiving the binary input signals and a second logic array having a plurality of output lines on which the binary output signals emanate. A first plurality of wordlines are provided which emanate from the first array. A second plurality of wordlines are provided which enter into the second array. A combinatorial logic unit is provided for processing binary signals emanating from the first array on the first plurality of wordlines before the binary signals emanating from the first array enter the second array on the second plurality of wordlines so that the programmed logic array implements a CASE statement.

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