Subchannel memory access control

Details Subchannel memory access control Subchannel memory access control

G - Physics

06

F

354/233

G06F 13/00 (2006.01) G06F 13/10 (2006.01)

Patent

CA 1057408

Abstract of the Disclosure Disclosed is a data processing system having channel equipment connected with input/output control unit(s) which is or are connected with a plurality of input/output devices and can control in parallel each input/ output device on a time sharing basis and other input/output control unit(s) which is or are connected with plural number of input/output devices and can control selectively the one of the pertinent input/output device and also having the memory unit. The plural number of unit control word memory domains are assigned corresponding to each input/out device to be controlled by the former input/output control unit(s) and one or plural number of unit control word memory domain(s) are assigned corresponding to the latter input/output control unit provided on the memory. A table means gives the address informa- tion of the former unit control word memory domain when being accessed accor- ding to the device number of each input/output device controlled by the former input/output control unit and also gives the address of the latter unit control word memory domain when being accessed according to the device number of the input/output device controlled by the latter input/out control unit.

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