Subtraction in a viterbi decoder

Details Subtraction in a viterbi decoder Subtraction in a viterbi decoder

H - Electricity

03

M

H03M 13/41 (2006.01)

Patent

CA 2353032

A Viterbi decoder for decoding a convolutional code. For each possible state, an accumulated error AE is maintained at 66. As each codeword Rx-GP is received, the errors between it and the code groups of all the transitions are determined at 65. For each possible new state, logic 68 determines the errors of the two transitions leading from old states to that new state, adds them to the accumulated errors of those two old states, and determines the smaller of the two sums. Path logic 67 records the corresponding transition, updating a record of the path leading to the new state. Tracing back along a path a predetermined and sufficiently large number of transitions, the input bit or bits corresponding to the transition so reached are taken as the next bit or bits in the stream of decoded bits. To renormalize the accumulated errors, the smallest accumulated error is determined by a minimum accumulated error determining unit 57 and subtracted from the errors from unit 65 by subtractors 80 before the additions and comparisons in logic 68. The unit 57 comprises a tree of comparators fed with the accumulated errors.

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