Superconducting memory array configurations which avoid...

Details Superconducting memory array configurations which avoid... Superconducting memory array configurations which avoid...

G - Physics

11

C

352/49

G11C 11/44 (2006.01)

Patent

CA 1109561

SUPERCONDUCTING MEMORY ARRAY CONFIGURATIONS WHICH AVOID SPURIOUS HALF-SELECT CONDITION IN UNSELECTED CELLS OF THE ARRAY Abstract of the Disclosure A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. For example, no circulating current can represent a binary zero, while a single circulating current can represent a binary one. In another instance, counter-rotating circulating currents can represent a binary one and a binary zero. The circulating current in combination with a half-select current, during writing of a selected memory cell, may, because of poor margins in adjacent memory cells, spuriously write information into an unselected memory cell when the half-select current is applied simultaneously to a number of memory cells which includes a selected memory cell. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell. Diversion of the enabling current is, in turn, achieved by the switching -1- of a serially disposed Josephson device which switches in response to the presence of two half-select currents in that device. Any other similarly serially disposed device in an unselected memory cell en- counters only a single half-select current and, under such circumstances, cannot switch to control its associated storage gate. Any other un- selected cell encounters, at most, a single half-select current. In another arrangement, the initially applied half-select current enables a plurality of gates to which a second half select current can be applied. When the second-half select current is applied, only that enabled gate associated with the line to which the second half-select current is applied switches, diverting the second half-select current into another path which controls the storage device of only the selected cell.

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