Supervisor address key control system

Details Supervisor address key control system Supervisor address key control system

G - Physics

06

F

354/239

G06F 13/00 (2006.01) G06F 12/14 (2006.01)

Patent

CA 1075823

ABSTRACT OF THE DISCLOSURE System mode controls for obtaining limited address- ability for supervisor programming operations without dis- turbing a user address key currently contained in a user key register (UKR). The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest super- visor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory. However, if the APM bit is off while the supervisor bit is on, alI instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor. But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute. BC9-76-011

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