Suppressed clock extraction by a phase locked loop

Details Suppressed clock extraction by a phase locked loop Suppressed clock extraction by a phase locked loop

H - Electricity

03

L

328/28, 328/87

H03L 7/06 (2006.01) H03L 7/08 (2006.01)

Patent

CA 1179024

ABSTRACT OF THE DISCLOSURE A system for suppressed clock extraction by a phase locked loop is realized to extract clock signal from a digital suppressed clock modulation signal. The edge signal of the incoming data triggers a window generator's output high. The input signal is also delayed for a half clock period before applied to one input of a frequency/phase detector. The output of said window generator provides a control signal enabling an edge signal of feedback ? through a sampling latch. This windowed feedback signal is routed to another input of the frequency/phase detector. The output of the detector is further filtered by a low pass filter before being applied to an input of a voltage controlled oscillator. The output of the voltage controlled oscillator is the extracted clock signal acting also as the feedback signal. Due to the window effect applied to the feedback signal, there will be phase comparison by the frequency/ phase detector only when input data edge signal is available.

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