Switch with one-bit resolution

H - Electricity – 04 – Q

Patent

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Details

H04Q 11/04 (2006.01)

Patent

CA 2230928

The invention relates to implementing switching in a switch in a digital telecommunications system. N incoming signals are introduced to the switch, each comprising successive one-bit time slots that form successive frames each comprising K time slots. The contents of the time slots for the incoming signals are stored in a memory at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location. One word at a time is read out from the memory, wherefrom the desired bit is selected for the outbound signal from the switch. To optimize the size and power consumption of the switch, the incoming signals are distributed to X multiplexers (A1...A x), each interleaving the incoming signals thereto into a single serial output signal (IN1...INX), and writing into memory is carried out by writing the contents of the time slots of the output signals into the same memory location having a width of at least X bits, the memory location changing from one time slot of the output signals of the multiplexers to another.

L'invention concerne la mise en oeuvre d'une commutation dans un commutateur d'un système numérique de télécommunications. On introduit dans le commutateur N signaux entrants, comprenant chacun des créneaux temporels successifs à un bit constituant des trames comprenant chacune K créneaux temporels. Le contenu des créneaux temporels concernant les signaux entrants sont stockés dans un emplacement de mémoire déterminé par une adresse d'écriture de manière à ce qu'un mot d'une longueur d'au moins un bit soit stocké dans un emplacement de mémoire. On extrait de la mémoire les mots un par un, à partir de quoi on sélectionne le bit désiré pour le signal à destination de l'extérieur en provenance du commutateur. Afin d'optimiser la taille et la consommation d'énergie du commutateur, les signaux entrants sont répartis entre X multiplexeurs (A1...Ax), chacun d'eux imbriquant les signaux entrants dans un unique signal de sortie sériel (IN1...INX) tandis que l'entrée en mémoire est réalisée par l'écriture du contenu des créneaux temporels des signaux de sortie dans le même emplacement de mémoire d'une longueur d'au moins X bits, l'emplacement de mémoire changeant d'un créneau temporel des signaux de sortie des multiplexeurs à un autre.

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