H - Electricity – 03 – F
Patent
H - Electricity
03
F
330/41
H03F 1/30 (2006.01)
Patent
CA 1289205
SYMMETRIC INTEGRATED AMPLIFIER WITH CONTROLLED DC OFFSET VOLTAGE: Abstract A symmetric integrated FET amplifier (e.g., 30) is disclosed which exhibits a DC offset voltage that is insensitive to power supply variations, as well as variations in the threshold voltages of the FETs forming the amplifier. These variations are known to be most prevalent in InP-based FET amplifier arrangements. The symmetry is achieved by using a pair of impedance matching elements (e.g., 44, 46) in the input stage of the amplifier to essentially match the impedance of the input FET and its load element; a matching buffer FET (e.g., 48) and diode level shifting arrangement (e.g., 50) are used to match similar elements present in the output branch of the amplifier structure. The impedance matching elements, as well as the level shifting diodes, may all be formed with FET structures to minimize fabrication problems. In accordance with the symmetric arrangement of the present invention, the output DC offset voltage will be maintained at zero volts, regardless of the variations noted above. A multistage symmetric amplifier may then be formed simply by directly connecting a number of single stage symmetric amplifiers together in series.
600924
American Telephone And Telegraph Company
Kirby Eades Gale Baker
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