Symmetric multi-processing control arrangement

Details Symmetric multi-processing control arrangement Symmetric multi-processing control arrangement

G - Physics

06

F

354/231, 354/241

G06F 9/46 (2006.01)

Patent

CA 1315411

ABSTRACT OF THE DISCLOSURE A digital data processing system including a plurality of processors, each including a central processor unit for processing programs at predetermined synchronization priority levels and a cache memory. A memory shared by all of the processors includes an synchronization level table which identifies a processor operating at each synchronization priority level. A common bus interconnects the processors and the memory. When a processor is to execute a program, it adjusts its synchronization priority level to a predetermined synchronization priority level. To do that, the processor accesses the synchronization level table over the common bus to determine whether the level is accessible and, if so, places an entry in the table to indicate that the synchronization priority level is occupied. If the synchronization priority level is not accessible, the processor continually monitors the entry in the table over the common bus to determine when it is accessible. To accomplish that, the processor monitors its cache, which contains a copy of the table entry associated with the synchronization priority level. When the synchronization priority level becomes accessible, the cache copy is invalidated so that the processor then has to use the table. Until the synchronization priority level does become accessible, however, the processor uses the cache copy of the table entry which reduces accesses of memory.

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