H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 27/10 (2006.01) H01L 27/118 (2006.01)
Patent
CA 2114790
A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell (100) includes a four transistor arrangement in which a substrate tap (308) is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps (304, 308, 314) outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns (302, 306, 310, 312) for the sharing of substrate taps (308) between pairs of columns. This mirroring feature further reduces routing complexity.
L'invention concerne une architecture de matrice de portes logiques prédiffusées dont la surface de silicium est nettement inférieure à celle utilisée jusqu'à maintenant. La cellule de la matrice (100) se compose d'un montage à quatre transistors dans lequel une bande de connexion au niveau du substrat (308) est adjacente à la paire de transistors. On obtient ainsi une matrice de cellules plus "symétrique" que ce qui existait auparavant. En plaçant les bandes de connexion (304, 308, 314) à l'extérieur des transistors, les interconnexions des lignes d'alimentation peuvent être acheminées facilement et efficacement. De plus, cette architecture de matrice de portes met en symétrie les paires de colonnes de transistors (302, 306, 310, 312), ce qui permet de partager les bandes de connexion (308) entre les paires de colonnes. Cette caractéristique de symétrie permet de réduire encore la complexité du routage.
Aspec Technology Inc.
Dimock Stratton Llp
LandOfFree
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