Symmetrical multi-layer metal logic array with continuous...

Details Symmetrical multi-layer metal logic array with continuous... Symmetrical multi-layer metal logic array with continuous...

H - Electricity

01

L

H01L 27/118 (2006.01) H01L 27/105 (2006.01)

Patent

CA 2126479

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Architecture de réseau de portes utilisant considérablement moins d'espace sur la puce de silicium que les réseaux de portes actuels. La cellule principale présente une configuration à quatre transistors. Une prise reliée à un substrat est aménagée près des paires de transistors, ce qui permet d'obtenir un réseau de portes plus «symétrique» que les réseaux de portes classiques. La disposition des prises à l'extérieur des transistors permet de disposer simplement et efficacement les connexions d'alimentation. L'architecture comprend une partie rallongée dans la région de contact de la cellule pour réduire davantage la complexité des câblages. En outre, l'architecture du réseau de portes reproduit exactement les paires de colonnes de transistors, ce qui permet de partager les prises reliées au substrat entre les paires de colonnes. Cette disposition symétrique réduit encore davantage la complexité des connexions.

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