Synchronization adder circuit

Details Synchronization adder circuit Synchronization adder circuit

G - Physics

06

G

G06G 7/14 (2006.01) H04L 5/06 (2006.01) H04L 7/02 (2006.01)

Patent

CA 2131770

A synchronization adder circuit for digital data communication is provided. This circuit includes an A/D converter, a waveform-shaping circuit, a square circuit, a low-pass filter, and an adder. The A/D converter samples at given sampling points in time per sampling cycle a received signal transmitted through a plurality of subcarriers to digitize sampled values to provide digital signals. The waveform-shaping circuit then waveform-shapes the digital signals from said A/D converter without decomposing them with respect to each subcarrier. The square circuit squares the output signals from the waveform-shaping circuit. The low-pass filter removes a given high-frequency component from output signals from the square circuit. The adder adds values of output signals from the low-pass filter at each sampling point for preselected sampling cycles to determine the samples suitable for reproduction of original data.

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