Synchronization and error detection in a tdm/tdma system

Details Synchronization and error detection in a tdm/tdma system Synchronization and error detection in a tdm/tdma system

H - Electricity

04

J

H04J 3/06 (2006.01) H03M 13/33 (2006.01) H04L 1/00 (2006.01) H04L 5/22 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2169514

A method and apparatus for bit synchronization and error detection uses bit rotation of a received data burst and division by a polynomial generator to produce a syndrome. Syndrome corrector logic steps and circuitry determine the bit slippage and correct the syndrome for the slippage to produce an error syndrome. If there are no errors, the bit slippage value is used to synchronize the received data burst.

L'invention est constituée par une méthode et un appareil de synchronisation des bits et de détection des erreurs qui utilise une permutation circulaire des bits d'une salve de données reçue et une division par un générateur polynomial pour produire un syndrome. Des opérations logiques et un circuit de correction de syndromes déterminent la dérive des bits dans le syndrome et la corrigent pour produire un syndrome d'erreur. S'il n'y a pas d'erreur, la valeur de dérive est utilisée pour synchroniser la salve de données reçue.

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