G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.5, 354/2
G06F 9/30 (2006.01) G06F 11/16 (2006.01) G06F 11/18 (2006.01) G06F 13/00 (2006.01) G11C 29/00 (2006.01)
Patent
CA 2003338
ABSTRACT: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
Allison John D.
Cutts Richard W. Jr.
Debacker Kenneth C.
Horst Robert W.
Jewett Douglas E.
Allison John D.
Cutts Richard W. Jr.
Debacker Kenneth C.
Gowling Lafleur Henderson Llp
Horst Robert W.
LandOfFree
Synchronization of fault-tolerant computer system having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronization of fault-tolerant computer system having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronization of fault-tolerant computer system having... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1761108