Synchronized clock using a non-pullable reference oscillator

Details Synchronized clock using a non-pullable reference oscillator Synchronized clock using a non-pullable reference oscillator

H - Electricity

03

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H03L 7/16 (2006.01) H03L 7/099 (2006.01) H03L 7/18 (2006.01) H03L 7/197 (2006.01) H03L 7/23 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2125441

Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-looked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency fitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual fitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

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