Synchronizing and processing of memory access operations in...

G - Physics – 06 – F

Patent

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354/233, 354/230

G06F 9/46 (2006.01) G06F 15/16 (2006.01)

Patent

CA 1324837

1 ABSTRACT OF THE DISCLOSURE An efficient synchronizing scheme is provided for processing "locked" memory access requests from various system units, including central processor units (CPUs) and (I/O units), in a high performance, multi-processing computer system. The processing is handled in such a manner that requests are processed according to a locking granularity substantially less than that of the overall system memory while, at the same time, insuring that multiple requests are granted fair and quick access to desired locations in shared memory. All monitoring and control of lock requests is handled by a system control unit (SCU) which controls the parallel operation of the plurality of CPUs and I/O units relative to the common main memory of the system. Locking granularity is defined at the level of individual cache blocks for the system CPUs, and the cache blocks also represent the unit of memory allocation in the computer system being services by the SCU. The synchronizing scheme operates by interlocking, as a unit, blocks of memory containing designated memory locations. The SCU is provided with a lock directory defined by a plurality of lock bits in such a way that each memory address associated with a memory access request is mapped to a corresponding location in the lock directory. The mapping is such that addresses in the same block of memory are mapped to the same location in the block directory. Incoming lock requests for a given memory location are processed by interrogating the corresponding lock bit in the lock directory in the SCU by using the associated memory address as an index into the directory. If the lock bit is not set, the lock request is granted. The lock bit is subsequently set and 2 maintained in that state until the unit requesting the lock has completed its memory access operation and send "unlock" request. If the interrogated lock bit is found to be set, the lock request is denied and the requesting port is notified of the denial and requested to try back again. A predefined degree of fairness is incorporated in the processing of denied lock requests by the definition of a reserve list onto which denied requests are sequentially positioned on a first-come-first-served basis.

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