Synchronizing circuit

H - Electricity – 04 – L

Patent

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Details

H04L 7/00 (2006.01) H04L 7/02 (2006.01)

Patent

CA 2057831

A synchronizing circuit to synchronize a digital input signal (DIN) with a clock signal (CK1) includes a detection circuit (DC) which checks if a present (SA) sample of a clock signal (CK3) being synchronized with the digital input signal, is equal to the previous (SB) sample, both samples being taken at an interval equal to the period (T) of the clock signal synchronized with the output signal. When the samples differ, the detection circuit generates a phase adjustment signal (CLR), which triggers a phase adjustment circuit (PAC) to ensure a return to synchronism by phase shifting the signal (ES) controlling the sampling of the digital input signal.

Circuit synchronisateur permettant de synchroniser un signal d'entrée numérique (DIN) avec un signal d'horloge (CK1). Comprend un circuit de détection (DC) qui vérifie si un échantillon (SA) d'un signal d'horloge (CK3) synchronisé avec le signal d'entrée numérique est égal à l'échantillon précédent (SB), les deux échantillons étant saisis à un intervalle égal à la période (T) du signal d'horloge synchronisé avec le signal de sortie. Lorsque les échantillons diffèrent, le circuit de détection génère un signal de réglage de phase (CLR), qui déclenche un circuit de réglage de phase (PAC) afin d'assurer un retour au synchronisme par déphasage du signal (ES) commandant l'échantillonnage du signal d'entrée numérique.

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