Synchronizing circuit for reducing waiting-time jitter in a...

Details Synchronizing circuit for reducing waiting-time jitter in a... Synchronizing circuit for reducing waiting-time jitter in a...

H - Electricity

04

J

363/17

H04J 3/06 (2006.01) H04J 3/07 (2006.01)

Patent

CA 2005194

There are time-division multiplex communication systems in which digital signals which are asynchronous with the pulse frame and consist of successive blocks whose beginnings are marked with sync words are inserted into the pulse frame. The resulting jitter of the sync words ("waiting-time jitter") is reduced by a circuit which derives from the clock of the received sync words a sync signal (SY) that exhibits less jitter than the clock of the received sync words. According to the invention, the circuit contains a measuring device which measures the time intervals (N) between the sync words, a filter (F) which takes the average (N') of the time intervals (N), and a signal generator (S) which forms the sync signal (SY) from said average (N') in such a manner that the pulse period of the sync signal (SY) is equal to said average (N').

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