Synchronous binary multiply using non-threshold logic

Details Synchronous binary multiply using non-threshold logic Synchronous binary multiply using non-threshold logic

G - Physics

06

F

354/214

G06F 7/50 (2006.01) G06F 7/52 (2006.01) H01L 27/07 (2006.01)

Patent

CA 1048651

- 1 - HIGH DENSITY MULTIPLIER George W. McIver James L. Buie ABSTRACT OF THE DISCLOSURE A sequential-add multiplier possessing high operating speed and high packing density in integrated form employs non-threshold logic to form a full adder at each one of its computational nodes. The full adder is made up of a combination of pnp multiple emitter transistors in emitter follower configuration forming eight AND gates coupled to a combination of npn multiple emitter transistors in emitter follower configuration forming four OR gates. - 1 -

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