Synchronous bus arbiter

Details Synchronous bus arbiter Synchronous bus arbiter

H - Electricity

04

L

340/84

H04L 13/00 (2006.01) G06F 13/374 (2006.01)

Patent

CA 1180410

ABSTRACT OF THE DISCLOSURE A bus arbiter resolves completing requests for access to a bus through local signal control lines that are coupled to an associated "master" (user of the bus) and control lines of the bus common to all other units. The control lines include identification lines defining the address and priority rank of the master, a request line for access to the bus, a grant line indicating control of the bus, and a release line through which a master releases control of the bus. Control lines common to other units include a busy line (indicating use of the bus), a bus clock line (for synchronization) a set of bus requests lines for handling address signals, and a select acknowledgement line used to terminate priority resolution. Each bus exchange control circuit contains a set of combinational logic which carries out housekeeping chores using the control signal lines, so as to enable its associated master to gain control of the bus when requested and, in the event of simultaneous requests, to resolve those requests in favor of the master having the highest priority.

393928

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