Synchronous demultiplexer for a t.d.m. signal

Details Synchronous demultiplexer for a t.d.m. signal Synchronous demultiplexer for a t.d.m. signal

H - Electricity

04

J

363/10

H04J 3/02 (2006.01) H04J 3/06 (2006.01) H04L 5/22 (2006.01)

Patent

CA 1200931

ABSTRACT: A SYNCHRONOUS DEMULTIPLEXER FOR A t.d.m. SIGNAL: A t.d.m. signal with a high bit rate and block-form frame code word is distributed between a plurality of channels (3 to 6) in a demulitplexer (2) by means of a chain circuit composed of conductor elements (32 to 35). The connected transmission path comprises stores (7, 8, 10) and a channel distributor (9). The channel distributor (9) is controlled by the second store (7) via a decoder (15), stores (16, 17) and a coder (18). A logic-linking arrangement (21) and a frame counter (23) permit resynchronisation only when the frame code word has failed to appear four times consecutively. The synchronous demultiplexer facilitates high-speed operation at bit rates of 140 Mbit/s and 565 Mbit/s and likewise facilitates construction in ECL integrated circuit technology. (Figure 1)

434321

Affiliated with

Also associated with

Rating

Synchronous demultiplexer for a t.d.m. signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous demultiplexer for a t.d.m. signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous demultiplexer for a t.d.m. signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1283353