Synchronous digital signal to asynchronous digital signal...

H - Electricity – 04 – L

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H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04J 3/07 (2006.01) H04L 12/20 (2006.01)

Patent

CA 2063930

Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous signal, e.g., a Conference of European Posts and Telecommunications (CEPT)-4 signal, from a received synchronous signal, e.g., a Synchronous DigitalHierarchy (SDH) Synchronous Transport Module (STM)-1 signal. The improved jitterperformance results from employing a unique gap generator which causes gaps in areceived data signal to be spread regularly in time, and allows for almost continuous control by numerical techniques of the phase of a smooth output clock being generated. Phase control is obtained by employing a filtered version of the difference between the actual number of data bits in the received digital signal and the expected nominal number.

On peut améliorer la performance en cas de sautillement dans un désynchronisateur utilisé pour obtenir un signal asynchrone (CEPT)-4 (« Conference of European Posts and Telecommunications ») à partir d'un signal STM-1 (« Synchronous Transport Module ») à hiérarchie numérique synchrone. Cette performance améliorée résulte de l'utilisation d'un générateur de vides particulier qui étale uniformément dans le temps les vides dans les signaux de données reçus et permet d'obtenir au moyen de méthodes numériques un contrôle quasi continu de la phase du signal d'horloge en cours de production. Cette phase est commandée au moyen d'une version filtrée de la différence entre le nombre réel de bits de données dans le signal numérique reçu et le nombre nominal prévu.

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