Synchronous memory

Details Synchronous memory Synchronous memory

G - Physics

11

C

G11C 7/00 (2006.01) G11C 7/10 (2006.01) G11C 7/22 (2006.01)

Patent

CA 2297878

A synchronous single port random access memory comprises a core 2 of memory cells 3 arranged as rows and columns. The rows are addressed by a row decoder 5 and the memory cell outputs are connected as columns to a column decoder and multiplexer 7. The decoder and multiplexes 7 selects groups of memory cells 3 from the addressed row and connects these to sense amplifiers 8. Changes in address are propagated immediately to the core 2 so that the selected memory cells 3 are connected as quickly as possible and without any fixed delays to the sense amplifiers 8. Similarly, a read clock "rclk" enables the sense amplifiers 8 immediately upon becoming active.

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