System and method for draining an instruction pipeline

G - Physics – 06 – F

Patent

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G06F 9/46 (2006.01) G06F 9/38 (2006.01) G06F 15/16 (2006.01)

Patent

CA 2060555

P09-91-013 SYSTEM AND METHOD FOR DRAINING AN INSTRUCTION PIPELINE ABSTRACT The present invention comprises a system and method for selectively draining an instruction pipeline. In one embodiment, the invention is implemented in the context of pipelined processor having an interpretive storage and multiple execution units. In the described system, the instructions held in the interpretive storage are referred to as "milli-instructions" and the interpretive execution mode is referred to as "milli-mode". Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These private milli-mode instructions augment the architected instruction set. Milli-mode routines can intermingle the milli-mode only instructions with architected instructions to implement complex functions. In order to provide an enhanced level of flexibility and efficiency, the above-described embodiment includes a milli-instruction that causes the pipeline to drain. This milli-instruction, called DRAIN INSTRUCTION PIPELINE (DIP) allows greater selectivity by the coder over (1) when to drain the pipeline and (2) what type of pipeline drain to perform. In the preferred embodiment, the DIP instruction enables the coder to cause the system to suspend decoding until a selected event occurs. Specifically, the instruction includes options to suspend decoding until a selected one of the following events has occurred: all conceptually previous macro instructions have completed; all conceptually previous milli-code instructions have completed; all conceptually previous instructions have completed; all store requests have reached the point where no exceptions will occur, but the actual store may not have completed; all conceptually previous stores from all conceptually previous units-of-operation have completed (serialize); or invalidate instruction buffers and fetch the next sequential macro-instructions.

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