G - Physics – 01 – R
Patent
G - Physics
01
R
G01R 31/3181 (2006.01) G01R 31/28 (2006.01) G11C 29/00 (2006.01) H04W 88/02 (2009.01) H04N 17/00 (2006.01)
Patent
CA 2419939
The invention disclosed herein is a system and method for testing integrated circuit devices, including memory chips. The devices under test are subject to behavioural testing, in which a copy of signals in an application system is directed to the device under test, or to an electronic component connected to the device under test. This permits the device under test to be tested under the operating conditions of the application system, which is preferably similar to the actual application environment in which the device under test will ultimately be used. Conventional tests, including pattern testing and/or parametric tests, may also be performed on devices under test, if desired.
L'invention porte sur un système et sur un procédé de test de dispositifs à circuits intégrés comprenant des puces à mémoire. Ces dispositifs sont soumis à un test de comportement selon lequel une copie des signaux d'un système d'application est envoyée au dispositif subissant le test ou à un composant électronique connecté à ce dispositif. Ceci permet de tester le dispositif dans des conditions de fonctionnement du système d'application qui sont de préférence similaires à l'environnement d'application réel dans lequel le dispositif sera utilisé ultérieurement. Des tests traditionnels tels que des tests de motifs et/ou de paramètres peuvent être également réalisés sur les dispositifs subissant ce test.
Bereskin & Parr Llp/s.e.n.c.r.l.,s.r.l.
Concord Idea Corp.
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