System and method for testing integrated circuits

Details System and method for testing integrated circuits System and method for testing integrated circuits

G - Physics

01

R

G01R 31/26 (2006.01) G01R 1/04 (2006.01)

Patent

CA 2564297

A module (236, 236') containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).

Module (236, 236') contenant un système de test intégré (108) qui comprend un ou plusieurs moteurs de mesure (200, 202) étroitement accouplés avec un moteur de calcul (208). Le ou les plusieurs moteurs de mesure disposent d~au moins un instrument d~excitation (212) pour exciter la circuiterie d~un dispositif sous test (104) avec un ou plusieurs signaux de stimulus et qui génère des données de mesure. Le moteur de calcul comprend une circuiterie logique de calcul (800) pour déterminer si la circuiterie du dispositif sous test passe ou échoue. Le système de test intégré inclut également un moteur de communications (204) qui permet des communications dans les 2 sens entre le matériel de test automatisé du système de test (116) et / ou une interface utilisateur spécialisée (140) située sur un serveur (136).

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