System clock synchronisation using phase-locked loop

Details System clock synchronisation using phase-locked loop System clock synchronisation using phase-locked loop

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/085 (2006.01) H03L 7/091 (2006.01) H03L 7/181 (2006.01) H04B 7/26 (2006.01) H04J 3/06 (2006.01) H04M 1/725 (2006.01) H04Q 7/32 (2006.01)

Patent

CA 2366495

An apparatus for synchronizing the system clocks of wireless devices in a digital communications system is presented. A digital phase-locked loop is employed. The phase-locked loop may include a counter which is incremented by a local device system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal. The phase-locked loop may alternatively include a counter that reflects the level of data stored in receive and/or transmit FIFO buffers. The loop output signal controls the frequency of the system clock oscillator.

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