System for controlling address keys under interrupt conditions

Details System for controlling address keys under interrupt conditions System for controlling address keys under interrupt conditions

G - Physics

06

F

354/239, 354/230

G06F 9/46 (2006.01)

Patent

CA 1075366

ABSTRACT OF THE DISCLOSURE A control circuit arrangement for storing the addressability currently being accessed by a processor by inputting and storing each processor active address key (AAK) in a last AAK register. When a hard or soft check interrupt occurs, the interrupted addressability is saved as the processor's last key saved (i.e LKSA) in the processor last AAK register. A hard or soft check interrupt includes a machine check interrupt, a program check interrupt, or a software exception. The interrupted addressability in then connected to the supervisor addressability by gating the LKSA into the source operand key section in the AKR from the processor's last AAK register, and setting the supervisor key into the other sections of the AKR, in preparation for performing certain supervisor operations. Until the LKSA gating into the AKR is completed, no AAK is ingated into the last AAK register. Thereafter the ingating by the last AAK register is resumed when the processor generates either a machine check reset, program check reset, or system reset.

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