System for controlling an internally-installed cache memory

Details System for controlling an internally-installed cache memory System for controlling an internally-installed cache memory

G - Physics

06

F

354/237

G06F 13/14 (2006.01) G06F 12/08 (2006.01) G06F 12/10 (2006.01)

Patent

CA 2034709

A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to an address translation. It has an address monitor portion having a tag portion corresponding to the tag portion of the CPU using only A bits of the offset portion of the set address which are used as the set address in the cache and having a 2B x N-way set associative structure and means for making said tag portion of the cache to correspond to said tag portion of the address monitor portion, thereby performing management of N address stored in the tag portion of the address monitor portion and transmitting the result of the management of the address to the cache and for invalidating corresponding recording portion of the tag in the cache.

Une mémoire cache utilise A bits d'une partie décalage qui ne sont pas assujettis à la traduction de l'adresse logique et B bits de la partie autre que la partie décalage, qui sont assujettis à une traduction d'adresse. Elle comporte une partie contrôle d'adresse qui comprend une partie étiquette correspondant à la partie étiquette du CPU utilisant seulement A bits de la partie décalage de l'adresse définie qui sont utilisés comme adresse définie dans la mémoire cache; et une structure associative définie à 2B x N voies. Des moyens permettent, d'une part, de faire correspondre ladite partie étiquette de la mémoire cache à ladite partie indicatrice de la partie contrôle d'adresse, ce qui assure la gestion de N adresses stockées dans la partie étiquette de la partie contrôle d'adresse et la transmission du résultat de la gestion de l'adresse à la mémoire cache, et, d'autre part, d'invalider la partie enregistrement correspondante de l'étiquette dans la mémoire cache.

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