System for fast selection of non-cacheable address ranges...

Details System for fast selection of non-cacheable address ranges... System for fast selection of non-cacheable address ranges...

G - Physics

06

F

354/241

G06F 12/08 (2006.01)

Patent

CA 1315011

SYSTEM FOR FAST SELECTION OF NON-CACHEABLE ADDRESS RANGES USING PROGRAMMEJD ARRAY LOGIC ABSTRACT A fast logic system for decoding addresses for the purpose of designating areas of memory as non-cacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

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