System for generating mask pattern for vector data processor

Details System for generating mask pattern for vector data processor System for generating mask pattern for vector data processor

G - Physics

06

F

354/230.7

G06F 15/16 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1273113

SYSTEM FOR GENERATING MASK PATTERN FOR VECTOR DATA PROCESSOR ABSTRACT OF THE DISCLOSURE A system for generating a mask pattern for a vector data processor having at least a mask register and a vector register in which, when the value of the mask register is "1", a calculation is executed for the corresponding element of the vector register, and when the value of the mask register is "0", a calculation is not executed, in accordance with the so-called calcula- tional mask function. The system includes a designation unit for designating sequential i elements of "0" or "1" from the head element of the mask register and the subsequent sequential j elements of "1" or "0", and a control unit for rendering the i elements to be "0" or "1", the j elements to be "1" or "0", and the remain- ing entire elements to be all "0's" or all 1's, when "i" plus "j" is smaller than a vector length which is the object of calculation of a vector data operand for use in a vector instruction, and a desired mask pattern of "0" or '1" is able to be generated in the mask register.

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